Technical Staff Engineer-ASIC Design
Company DescriptionMicrochip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.Job DescriptionAs a member of Microchip's engineering community, your primary responsibility will be to design, simulate, and verify the SerDes PCS (Physical Coding Sublayer) and protocol specific supporting digital logic solutions for an advanced ASIC or FPGA. Microchip's designs are an SOC with various Hard and Soft IP blocks that support a large number of industry standard protocols.
Responsibilities:
General RTL and ASIC developmentDetailed module design, performance analysis and detailed specification creationParticipate in the RTL implementation, synthesis, formality check as well as ECO'sSupport post-layout timing closure and verificationParticipate in the investigation & assessment of emerging SerDes / Transceiver technologies & IPsImprove Data & Command processing bandwidth, reduce latencies & increase reliabilitySupport porting the design into test chips and emulation platformsSupport pre-tapeout verification and post-tapeout validation / characterization of the system designedWork closely with FPGA support software and FW engineers to resolve hardware issues and customer issuesSerDes PCS DevelopmentIntegrate SERDES PMA and PCS Channels into a final design, including resets, clock domain crossing, power-down controls, calibration logic, and associated register mapsDevelop SPI and JTAG interfaces into PLL and PMA / PCS componentsDevelop Block Level Constraints and run synthesisPerform Test Chip Level Constraints and fun synthesisPerform Static Timing Analysis of the PCS. PLL control and full Test Chip blocks and review post - layout timingSupport Verification and Validation groups in testing of SERDES PMA and PCSDesign, simulate, and test encoder / decoder used in SERDES - based designs8B / 10B and similar encoders / decoders64B / 66B, 128B / 130B and similar encoders / decoderData Scramblers and other high speed datapath logicFEC encoders / decoders and associated test logicIntegrate and simulate SERDES - based designs includingDeveloping external interfaces to other parts of the system and / or FPGA fabricImplementing various control / status functions with associated register mapsDeveloping and Integrating AC / DC JTAG control interfacesDevelop and / or integrate to industry standard SerDes based protocol logicPCIe, Ethernet, MIPI, SDI, Interlaken, CEI, OTN, CPRI, PON, DisplayPort, HDMI, CoaxXpress, JESD204, USB, RapidIO, Fibre Channel, Optical Modules I/F, etcSerDes support logic such as power reduction algorithms, OOB signaling, CTLE and DFE calibration, etcSupport RTL design engineers with less experience for the functions shown aboveJob RequirementsBachelor's / Master's degree in Electrical Engineering, Computer Engineering or Computer ScienceMinimum of 15
years of proven silicon design experience in high speed RTL design of SerDes PCS and SerDes control / status / interface logicExperience is SOC IP development for SerDes PCS and associated protocolsStrong Experience in RTL design, design verification, synthesis & formalityStrong Experience in Static Timing Analysis and Verilog simulation toolsShould be able to design complex state machines & data path logicAbility to write detailed design specificationsGood analytical, oral and written communication skillsAble to write clean, readable presentationsSelf-motivated, proactive team playerAbility to work to schedule requirementsBeneficial Experience FPGA and ASIC System On Chip Design ExperienceLab Experience for System Level Validation#ZR
Salary Range:
$200K -- $250K
Minimum Qualification
Electrical EngineeringEstimated Salary: $20 to $28 per hour based on qualifications.
Responsibilities:
General RTL and ASIC developmentDetailed module design, performance analysis and detailed specification creationParticipate in the RTL implementation, synthesis, formality check as well as ECO'sSupport post-layout timing closure and verificationParticipate in the investigation & assessment of emerging SerDes / Transceiver technologies & IPsImprove Data & Command processing bandwidth, reduce latencies & increase reliabilitySupport porting the design into test chips and emulation platformsSupport pre-tapeout verification and post-tapeout validation / characterization of the system designedWork closely with FPGA support software and FW engineers to resolve hardware issues and customer issuesSerDes PCS DevelopmentIntegrate SERDES PMA and PCS Channels into a final design, including resets, clock domain crossing, power-down controls, calibration logic, and associated register mapsDevelop SPI and JTAG interfaces into PLL and PMA / PCS componentsDevelop Block Level Constraints and run synthesisPerform Test Chip Level Constraints and fun synthesisPerform Static Timing Analysis of the PCS. PLL control and full Test Chip blocks and review post - layout timingSupport Verification and Validation groups in testing of SERDES PMA and PCSDesign, simulate, and test encoder / decoder used in SERDES - based designs8B / 10B and similar encoders / decoders64B / 66B, 128B / 130B and similar encoders / decoderData Scramblers and other high speed datapath logicFEC encoders / decoders and associated test logicIntegrate and simulate SERDES - based designs includingDeveloping external interfaces to other parts of the system and / or FPGA fabricImplementing various control / status functions with associated register mapsDeveloping and Integrating AC / DC JTAG control interfacesDevelop and / or integrate to industry standard SerDes based protocol logicPCIe, Ethernet, MIPI, SDI, Interlaken, CEI, OTN, CPRI, PON, DisplayPort, HDMI, CoaxXpress, JESD204, USB, RapidIO, Fibre Channel, Optical Modules I/F, etcSerDes support logic such as power reduction algorithms, OOB signaling, CTLE and DFE calibration, etcSupport RTL design engineers with less experience for the functions shown aboveJob RequirementsBachelor's / Master's degree in Electrical Engineering, Computer Engineering or Computer ScienceMinimum of 15
years of proven silicon design experience in high speed RTL design of SerDes PCS and SerDes control / status / interface logicExperience is SOC IP development for SerDes PCS and associated protocolsStrong Experience in RTL design, design verification, synthesis & formalityStrong Experience in Static Timing Analysis and Verilog simulation toolsShould be able to design complex state machines & data path logicAbility to write detailed design specificationsGood analytical, oral and written communication skillsAble to write clean, readable presentationsSelf-motivated, proactive team playerAbility to work to schedule requirementsBeneficial Experience FPGA and ASIC System On Chip Design ExperienceLab Experience for System Level Validation#ZR
Salary Range:
$200K -- $250K
Minimum Qualification
Electrical EngineeringEstimated Salary: $20 to $28 per hour based on qualifications.
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