Design-for-Test (DFT) Implementation Engineer - DFT Solutions Team
Job Details:
Job Description:
Do Something Wonderful! Intel put the Silicon in Silicon Valley.
No one else is this obsessed with engineering a brighter future.
Every day, we create world changing technology that enriches the lives of every person on earth.
So, if you have a big idea, let's do something wonderful together.
Join us, because at Intel, we are building a better tomorrow.
Want to learn more? Visit our YouTube Channel or the links below! Life at Intel Diversity at IntelThe Network and Edge group (NEX) at Intel delivers the Infrastructure Processing Unit (IPU) which is shaping data center designs for the next decade.
Join the Network and Edge Group (NEX) to plan, develop and sell infrastructure acceleration solutions using Infrastructure Processing Units (IPU) in the Cloud, Telco and Enterprise market segments.
The Design-for-Test (DFT) Implementation Engineers of the DFT Solutions Team develop and deploy state-of-the-art DFT architectures, strategies, and flows and in turn use these creations to execute the DFT Implementation for current and next generation 5G Mobile Base-Station products.
You will be working with both external tier-1 customers and internal product design teams during their silicon design cycle as they develop System-on-a-Chip (SoC) solutions utilizing cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high-speed memory interface IP.
As a member of the Xeon and Networking Engineering Group (XNE) DFT Solutions Team, you are responsible for the holistic DFT Solution for a System-on-a-Chip (SoC) design and the below listed:
Development of the SoC Test Implementation plan to individualize the standardized DFT solutions to the SoC, including the hierarchical test architecture and the strategies to address SoC-specific DFT requirements.
Definition of the standardized DFT flow steps, deployment of the tool infrastructure and flow automation to implement the SoC DFT in a highly repeatable and predictable fashion.
Insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for High-Volume Manufacturing (HVM) testing of the design.
Development of the Static Timing Analysis (STA) constraints for physical construction and timing closure in all DFT modes, and collaboration with the Physical Design team to achieve timing closure for the DFT modes.
Collaborating with the HVM Test Engineering team during silicon bring-up and New Product Introduction (NPI).
Scaling the standardized DFT solutions to the wider XNE DFT Team across the products of the XNE portfolio.
The Design-for-Test (DFT) Implementation Engineer should possess the following attributes:
Excellent leadership skills, with the ability to guide, influence, and collaborate effectively with cross-functional teams and senior stakeholders.
Excellent communication skills to synthesize and create clear key messages backed by data.
Proven capacity to thrive and continuously learn in a dynamic, innovative setting, showcasing a growth mindset, quick adaptability, and a strong commitment to efficient execution.
Demonstrated thought leadership and cross-group collaboration skills.
A team player willing to jump in where needed as an active contributor.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
What we need to see (Minimum Qualifications):
Candidate must possess a BS in Electrical or Computer Engineering and 6
yrs.
exp.
OR MS in Electrical or Computer Engineering and 4
yrs.
experience in:
SoC Design-For-Test (DFT) principles such as SCAN for logic testing, BIST and repair for memory test, Boundary SCAN, Test insertion, test pattern generation, and verification.
Industry-standard DFT tools such as Siemens Tessent DFT, Synopsys DFT Compiler, DFTMax, TetraMax.
How to Stand out (Preferred Qualifications):
Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience.
Experience with the DFT integration of IP (e.
g.
DDR, SerDes, PLL's) into an SoC.
Experience with IEEE1149 JTAG Boundary SCAN, IEEE1687 IJTAGStatic Timing Analysis, Synopsys PrimeTime, constraints and timing path debug.
Programming skills; experience writing routines for data manipulation using advanced data structures; languages include PERL, Tcl/Tk.
DFT architecture development and planning for an SoC.
Amazing Benefits!Here at Intel, we invest in our people.
Beyond health, dental, and retirement benefits, Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment.
Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program.
Find more information about our Amazing Benefits here:
https:
//jobs.
intel.
com/benefitsJob Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, Pennsylvania, AllentownAdditional Locations:
US, California, Folsom, US, California, Santa Clara, US, Massachusetts, Hudson, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of TrustN/A
Benefits:
We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California:
$144,501.
00-$217,311.
00Salary range dependent on a number of factors including location and experience.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
SummaryLocation:
US, Pennsylvania, Allentown; US, Oregon, Hillsboro; US, Massachusetts, Hudson; US, California, Folsom; US, California, Santa Clara; US, Texas, AustinType:
Full time.
Estimated Salary: $20 to $28 per hour based on qualifications.
Job Description:
Do Something Wonderful! Intel put the Silicon in Silicon Valley.
No one else is this obsessed with engineering a brighter future.
Every day, we create world changing technology that enriches the lives of every person on earth.
So, if you have a big idea, let's do something wonderful together.
Join us, because at Intel, we are building a better tomorrow.
Want to learn more? Visit our YouTube Channel or the links below! Life at Intel Diversity at IntelThe Network and Edge group (NEX) at Intel delivers the Infrastructure Processing Unit (IPU) which is shaping data center designs for the next decade.
Join the Network and Edge Group (NEX) to plan, develop and sell infrastructure acceleration solutions using Infrastructure Processing Units (IPU) in the Cloud, Telco and Enterprise market segments.
The Design-for-Test (DFT) Implementation Engineers of the DFT Solutions Team develop and deploy state-of-the-art DFT architectures, strategies, and flows and in turn use these creations to execute the DFT Implementation for current and next generation 5G Mobile Base-Station products.
You will be working with both external tier-1 customers and internal product design teams during their silicon design cycle as they develop System-on-a-Chip (SoC) solutions utilizing cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high-speed memory interface IP.
As a member of the Xeon and Networking Engineering Group (XNE) DFT Solutions Team, you are responsible for the holistic DFT Solution for a System-on-a-Chip (SoC) design and the below listed:
Development of the SoC Test Implementation plan to individualize the standardized DFT solutions to the SoC, including the hierarchical test architecture and the strategies to address SoC-specific DFT requirements.
Definition of the standardized DFT flow steps, deployment of the tool infrastructure and flow automation to implement the SoC DFT in a highly repeatable and predictable fashion.
Insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for High-Volume Manufacturing (HVM) testing of the design.
Development of the Static Timing Analysis (STA) constraints for physical construction and timing closure in all DFT modes, and collaboration with the Physical Design team to achieve timing closure for the DFT modes.
Collaborating with the HVM Test Engineering team during silicon bring-up and New Product Introduction (NPI).
Scaling the standardized DFT solutions to the wider XNE DFT Team across the products of the XNE portfolio.
The Design-for-Test (DFT) Implementation Engineer should possess the following attributes:
Excellent leadership skills, with the ability to guide, influence, and collaborate effectively with cross-functional teams and senior stakeholders.
Excellent communication skills to synthesize and create clear key messages backed by data.
Proven capacity to thrive and continuously learn in a dynamic, innovative setting, showcasing a growth mindset, quick adaptability, and a strong commitment to efficient execution.
Demonstrated thought leadership and cross-group collaboration skills.
A team player willing to jump in where needed as an active contributor.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
What we need to see (Minimum Qualifications):
Candidate must possess a BS in Electrical or Computer Engineering and 6
yrs.
exp.
OR MS in Electrical or Computer Engineering and 4
yrs.
experience in:
SoC Design-For-Test (DFT) principles such as SCAN for logic testing, BIST and repair for memory test, Boundary SCAN, Test insertion, test pattern generation, and verification.
Industry-standard DFT tools such as Siemens Tessent DFT, Synopsys DFT Compiler, DFTMax, TetraMax.
How to Stand out (Preferred Qualifications):
Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience.
Experience with the DFT integration of IP (e.
g.
DDR, SerDes, PLL's) into an SoC.
Experience with IEEE1149 JTAG Boundary SCAN, IEEE1687 IJTAGStatic Timing Analysis, Synopsys PrimeTime, constraints and timing path debug.
Programming skills; experience writing routines for data manipulation using advanced data structures; languages include PERL, Tcl/Tk.
DFT architecture development and planning for an SoC.
Amazing Benefits!Here at Intel, we invest in our people.
Beyond health, dental, and retirement benefits, Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment.
Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program.
Find more information about our Amazing Benefits here:
https:
//jobs.
intel.
com/benefitsJob Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, Pennsylvania, AllentownAdditional Locations:
US, California, Folsom, US, California, Santa Clara, US, Massachusetts, Hudson, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of TrustN/A
Benefits:
We offer a total compensation package that ranks among the best in the industry.
It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in US, California:
$144,501.
00-$217,311.
00Salary range dependent on a number of factors including location and experience.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
SummaryLocation:
US, Pennsylvania, Allentown; US, Oregon, Hillsboro; US, Massachusetts, Hudson; US, California, Folsom; US, California, Santa Clara; US, Texas, AustinType:
Full time.
Estimated Salary: $20 to $28 per hour based on qualifications.
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